|
|
|
|
LEADER |
00710cam a2200229 7i4500 |
001 |
0000012745 |
005 |
20150325090000.0 |
003 |
iicp-my |
005 |
20090512134900.0 |
008 |
090512 000 0 eng d |
020 |
|
|
|a 9780471983255
|
039 |
|
9 |
|y 200905121349
|z Azlin
|
090 |
0 |
0 |
|a 621.395
|b RUS
|
100 |
1 |
|
|a Rushton, Andrew
|
245 |
0 |
0 |
|a VHDL for logic synthesis / by Andrew Rushton.
|
250 |
|
|
|a 2nd ed..
|
260 |
|
|
|a Chichester ; New York : John Wiley & Sons, 1998.
|
300 |
|
|
|a xiii 375 p.: ill. ; 25 cm..
|
650 |
|
0 |
|a Logic design - Data processing.
|
650 |
|
0 |
|a Computer - aided design.
|
650 |
|
0 |
|a VHDL (Computer hardware description language).
|
999 |
|
|
|a 1000020602
|b Book
|c Green Spot
|